Pulse compressor for multiplexed noise codes

ABSTRACT

A pulse compressor for multiplexed noise codes generated with transposed code mate pairs and which comprise expanded noise codes of the code mates where the first expanded code is generated by delaying the inverse of one code mate by a predetermined time delay and adding it to the other code mate and wherein the second expanded code is generated by delaying the inverse of the other code mate, forming its complement and adding it to said one code mate. The means utilized comprises means for compressing the two expanded codes collectively by summing and differencing of the codes in a repetitive pipelined sequence until a final pair of codes are outputted which are lobeless and equal to the basic mate pair.

The invention described herein may be manufactured, used and licensed byor for the Government for governmental purposes without the payment tome of any royalties thereon.

CROSS REFERENCE TO RELATED APPLICATION

This invention is related to the co-pending application Ser. No. 449,029entitled, "Multiplexed Noise Code Generator Utilizing Transposed Codes"(CERCOM D-2037) filed in the name of Frank S. Gutleber, the presentinventor, on Dec. 13, 1982.

1. Field of the Invention

This invention relates generally to multiplexed noise codes havingautocorrelation functions which upon matched filter detection provide animpulse, i.e., a lobeless autocorrelation function and more particularlyto the compression of expanded multiplexed noise codes into a basic codemate pair which are lobeless.

2. Background of the Invention

Noise codes comprised of what is termed code mate pairs are well known.Such codes have autocorrelation functions which upon matched filterdetection provide lobeless impulse signals. It is also well known thattypical means of compressing such a code mate pair is to employ apassive matched filter in the form of a separate tapped delay line foreach code, with the output of the taps matched to the input code bits inreverse order to the input sequence. The linear summation of the matchedoutputs of each delay line then provides the compressed code for eachcode of the mate pair. Each output is equal to the autocorrelationfunction of the respective code being detected and the simple linear sumof the two outputs results in a lobeless compressed mate pair.

Such a configuration becomes relatively expensive and difficult toimplement for very long codes since a separate tap with or without aninverter is required for each bit of the input code. Such long codestypically comprise expanded codes from a basic code mate pair andtypically involves butting, interleaving, partial interleaving, oroverlapping one code mate with the other code mate where, for example,one of the codes is delayed by a value equal to the code length of thetwo mate pairs in the expansion process. A typical example of suchtechniques is shown and described in U.S. Pat. No. 3,461,451, entitled,"Code Generator To Produce Permutations Of Code Mates," issued to FrankS. Gutleber, the present inventor, on Aug. 12, 1969. Another examplecomprises codes generated in accordance with the invention disclosed inthe above referenced co-pending application entitled, "Multiplexed NoiseCode Generator Utilizing Transposed Codes," wherein expanded multiplexednoise codes including code mate pairs having autocorrelation functions,which upon detection provide an impulse autocorrelation function, aregenerated by delaying the inverse of one of the code mate pairs by avalue equal to the code length and adding it to the other code mate pairto form a first expanded code mate, while a second expanded code mate isgenerated by delaying the inverse of the other code also by a valueequal to the code length, forming the complement thereof and adding itto the first mentioned code mate, forming what is generally referred toas transposed codes. It is to this latter type of code generation thatthe present invention particularly pertains.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide animprovement in the detection of multiplexed noise codes.

Another object of the invention is to provide improvement in thecompression of multiplexed noise codes.

Still another object of the present invention is to provide animprovement in the compression of expanded multiplexed noise code pairs.

And yet another object of the present invention is to provide animprovement in the compression of expanded multiplexed noise codesgenerated with transposed codes of multiplexed noise code mate pairs.

These and other objects are achieved by a means for compressing a pairof expanded codes which have been generated from a basic code mate pairwhere the first expanded code is comprised of the combination of onecode mate and the inverse of the other while the other expanded code iscomprised of the combination of the other basic code mate and theinverse complement of the first code mate. Code compression of theexpanded code mate pairs is accomplished collectively rather thanindividually by a repetitive summing and subtracting process insuccessive stages whereby the coherent compression of the expanded codeback down to a lobeless basic mate pair is accomplished. In oneembodiment, one expanded mate pair is summed with the inverse of theother expanded mate pair, thereby forming a first compressed code mateof one half the original code length, while a second compressed codemate of half the code length is formed by differencing the secondexpanded code mate and the inverse of the first expanded code mate. In asecond embodiment, the compression is obtained with only a single codesequence inversion and appropriate time delays.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram illustrative of a first embodimentfor compressing expanded multiplexed noise code pair mates in accordancewith the subject invention; and

FIG. 2 is a functional block diagram illustrative of a second embodimentfor compressing expanded multiplexed noise code pair mates in accordancewith the subject invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention is directed to compression of a type of expandedmulti-bit digital codes referred to as noise codes, meaning that theyhave autocorrelation functions which upon detection provides an impulse.In particular, one class of noise codes are known wherein pairs of codedsignals termed "code mates" have respective autocorrelation functionswhich provide a peak output at a given time and a zero output or outputshaving the same magnitude but opposite polarity at all other times. Whencode mates, for example, are orthogonally multiplexed, matched filterdetected and linearly added, there is provided a lobeless impulse outputof a relatively high amplitude at a given time and a zero output at allother times.

Expressed mathematically, for a pair of code mates a and b, φ_(a)(τ)=-φ_(b) (τ) for all τ≠0, where φ_(a) (τ) is the autocorrelationfunction of code a and φ_(b) (τ) is the autocorrelation function of codeb.

The pulse compression to be subsequently described provides an improvedmeans for compressing to a lobeless impulse a multiplexed noise codepair for code mates that are expanded in accordance with the followingexpression:

    Code A=a, b                                                (1)

    Code B=b, a                                                (2)

Where A and B comprise an expanded code mate pair generated from Codes aand b which comprise a basic mate pair, and wherein: x is the inverse ofcode sequence x, i.e. x₁, x₂, x₃ becomes x₃, x₂, x₁ ; x0 is the negativeor complement of code x; and the (,) in a code sequence x, y signifiesthat the subelement or code sequence y follows code sequence x by sometime delay τ_(i).

In the expansion process of code mate pairs in accordance with equations(1) and (2), any one of the four subelements or code sequences (a, b, aor b) making up the expanded code can be inverted or complemented aswell as interchanged such that for example,

    Code A=a, b                                                (3)

    Code B=b, a                                                (4)

or,

    Code A=b, a                                                (5)

    Code B=a, b                                                (6)

In all such instances, the expanded code pairs A and B meet therequirements for forming a code mate pair.

In view of the foregoing, consider now the following code mate pair A=a₃and B=b₃ that is generated in accordance with repeated application ofthe expansion rules set forth in equations (1) and (2), bearing in mindthat expansions according to equations (3) through (6) could also beutilized, when desired. For a basic code mate pair a and b, a firstexpansion results in codes a₁, b₁ being developed as follows:

    a.sub.1 =a, b                                              (7)

    b.sub.1 =b, a                                              (8)

Expanding code mates a₁ and b₁ in a second expansion process provides amate pair a₂ and b₂, which can be expressed as follows:

    a.sub.2 =a.sub.1, b.sub.1 =a, b, a, b                      (9)

    b.sub.2 =b.sub.1, a.sub.1 =b, a, b, a                      (10)

A third expansion, involving now the code mates a₂ and b₂, results incode mates a₃ and b₃ being developed in the following manner:

    a.sub.3 =a.sub.2, b.sub.2 =a, b, a, b, a, b, a, b          (11)

    b.sub.3 =b.sub.2, a.sub.2 =b, a, b, a, b, a, b, a          (12)

As is known, having been shown and described, for example, in the abovereference related application Ser. No. 449,029, entitled, "MultiplexedNoise Code Generator Utilizing Transposed Codes," codes a₃ and b₃ form amate pair wherein φa₃ (τ)=-φb₃ (τ) for all τ≠0 and accordingly can becompressed to a lobeless impulse. The present invention accordingly isdirected to a means for compressing expanded code mate pairs such asdeveloped in equations (7) through (12) in a collective manner ratherthan individually, as in prior art practice, where separate tapped delaylines for each code are used and wherein the output of the taps of thedelay lines are matched to the input code bits in reverse order to theinput sequence providing thereby a complex conjugate of the input bits.

The present invention results from an inspection of the foregoingexpansion process which reveals that a repeated application of thefollowing general operation will coherently compress the expanded codemate back to a lobeless basic mate pair, namely:

    a.sub.i-1 =a.sub.i +b.sub.i                                (13)

    b.sub.i-1 =b.sub.i -a.sub.i                                (14)

An appropriate time delay τ_(i) is required to line up the compressedbits at each stage and/or account for the delay introduced with the codeinverter where, for example, the inverter comprises a last-in/first-out(LIFO) code sequence inverter.

Since equations (13) and (14) involve code inversions of the expandedcodes A=a₃ and code B=b₃ as expressed in equations (11) and (12),inverted sequences thereof, i.e. a₃ and b₃ can be expressed as follows:

    A=a.sub.3 =b, a, b, a, b, a, b, a                          (15)

    B=b.sub.3 =a, b, a, b, a, b, a, b                          (16)

Applying code compression equation (13) to codes a₃ and b₃ results in acode sequence a₂ being obtained which is one half the code length of a₃and which is formed as illustrated below as: ##EQU1## where the exponentindicates the amplitude of the respective codes.

In a like manner, the code mate b₂ is developed in accordance withequation (14) in the following manner: ##EQU2##

The inversion process in developing equation (17) means inverting notonly the code sequence of b₃ but also changing all the subelements sothat, for example, x becomes x and x becomes x. In the differenceequation (18) the subtracted term, i.e. a₃ is complemented such that xbecomes x0 and x0 becomes x and a summation is thereafter made.

Similarly, compressed code mates a₁ and b₁ are obtained in accordancewith the foregoing mathematical operations as follows: ##EQU3## and,##EQU4##

A third compression results in providing the basic code mates a and bbut whose amplitude is amplified by a factor of 8. This is obtained asshown below: ##EQU5## and, ##EQU6##

Referring now to FIG. 1, there is disclosed a functional block diagramof means which is operable to compress the expanded code mate pair a₃and b₃ in conformance with equations (13) and (14). As shown, the codecompressor is comprised of a combination of linear adders,last-in/first-out (LIFO) shift registers which operate as sequenceinverters to invert a sequence where, for example, x₁, x₂, x₃ becomesx₃, x₂, x₁ and signal inverters which operate to provide the complementof the input code, for example, x becomes x

The compressor shown in FIG. 1 is comprised of three compressor stages10₁, 10₂ and 10₃. The first stage 10₁ is shown coupled to a pair ofinput codes comprising the code mate pair a₃ and b₃ which is compressedin stage 10₁ to half their respective lengths by means of a linear adder12₁ and a LIFO shift register 14₁ directly coupled to the expanded codemate a₃ while the other code mate b₃ is directly coupled to a secondlinear adder 16₁ and a second LIFO shift register 18₁. A signal inverter20₁ is coupled between the LIFO shift register 14₁ and a second linearadder 16₁. A clock 22 is coupled to the two LIFO shift registers 14₁ and18₁ in order to control the read in and read out times of the codesequences of a₃ and b₃, respectively. It can be seen that the linearadder 12₁ is operable to add the inverted sequence of code b₃ to thesequence of a₃ and thus implement equation (13) and output a compressedcode mate a₂. Code a₃ has its bit sequence inverted in the LIFO shiftregister 14₁, is complemented with the signal inverter 20₁ and added tocode b₃ in the linear adder 16₁ to implement equation (14) and output acompressed code mate b₂.

In a similar manner, the once compressed code mates a₂ and b₂ are fed tothe second compressor stage 10₂ where a compressed code mate a₁ equal toone half the code length of a₂ is obtained by inverting the code b₂ andadding it to the code a₂. In a similar manner, the code sequence of a₂is inverted, complemented and added to the code b₂ to compress to thecode mate b₁. Duplicating this process once more in the third compressorstage 10₃ then compresses the code mate pairs a₁ and b₁ down to theoutput codes which comprise the basic code mate pairs a and b and whichare not only lobeless, but are obtained with significantly less hardwarethan what is required for conventional compressors.

It should be pointed out that only p compression stages are required tocompress an n bit code length down to a single impulse where 2^(p) =n.For example, only 10 compression stages would be required to compress a1024 bit noise code structure down to a lobeless impulse.

An alternative approach to the expanded code compression process willnow be described. Assuming for example that the previously disclosedcode mate pairs a₃ and b₃ require compression to a lobeless impulse, ifthe expanded code b₃ is first inverted to b₃, then a simple sum anddifference with appropriate delays at each subsequent stage willcompress the mate pair a₃ and b₃ down to the basic code mates a and b inthe following manner.

At the first stage the codes a₃ and b₃ are added as shown below toprovide the code a₂ as follows: ##EQU7##

Likewise, the code a₃ is subtracted from b₃ to provide the code b₂, as:##EQU8## In the next or second compression stage, the code a₂ is delayedby a time delay τ₂ to yield a code a'₂ which is illustrated below as:

    a'.sub.2 =a.sub.2 (t+τ.sub.2)=., ., ., ., a.sup.2,b.sup.2,a.sup.2,b.sup.2                           (25)

The codes a'₂ and b₂ are then summed in the following manner to providethe code a₁ : ##EQU9##

As before, the difference between codes b₂ and a'₂ yield the compressedcode b₁ which is illustrated below as: ##EQU10##

In the third compression stage, the compressed code a₁ is delayed by atime delay τ₁ to provide the code a'₁ which is illustrated below as:

    a'.sub.1 =a.sub.1 (t+τ.sub.1)=., ., ., ., ., ., a.sup.4, b.sup.4 (28)

As before, the compressed codes a'₁ and b₁ are summed together toprovide the basic code mate a which has an amplitude increased by afactor of 8 which is illustrated below as: ##EQU11##

Similarly, the codes b₁ and a'₁ are differenced to provide the basiccode mate b which also has an amplitude increased by a factor of 8 andwhich is also illustrated as: ##EQU12##

Referring now to FIG. 2, there is disclosed a functional block diagramof a circuit configuration which is operable to compress the expandedcode mate pair a₃ and b₃ in accordance with the above disclosedalternate approach. As shown in FIG. 2, the code compressor is comprisedof three compressor stages 24₁, 24₂ and 24₃. The first compressor stage24₁ is adapted to receive as inputs the expanded codes a₃ and b₃ whichcompress to half their code lengths by means of a pair of linear adders26₁ and 28₁ as well as a LIFO shift register 30₁ and a signal inverter32₁. The LIFO shift register 30₁ is coupled to and inverts the code b₃which is applied to the linear adder 26₁ along with the code a₃whereupon a compressed code a₂ is provided in accordance with equation(23). The input code a₃ is also applied to the inverter 32₁ where thecomplement thereof is applied to the second linear adder 28₁ along withthe inverted code b₃ to provide the compressed code output b₂ inaccordance with equation (24).

The second compressor stage 24₂ includes a first time delay means 34₂ inthe signal channel coupled to the linear adder 26₂. The LIFO shiftregister 30₁ which is included in the first stage 24₁, is not requiredand the compressed code b₂ is applied directly to the linear adders 26₂and 28₂. The time delay circuit 34₂ provides a time delay τ₂ which isequal to the code length of code b₂. The output of the delay circuit 34₂is applied as the code a'₂ to the inverter 32₂ and the linear adder 26₂.The linear adder 26₂ accordingly operates to combine the codes a'₂ andb₂ to provide the compressed code a₁ in accordance with equation (26).The linear adder 28₂ adds the complement of the code a'₂ to the code b₂to provide an output of the compressed code b₁ in accordance withequation (27).

The third compressor stage 24₃ is identical in configuration to thesecond compressor stage 24₂ with the exception that the time delay means34₃ provides a time delay of τ₁ =0.5 τ₂ and provides an output code a'₁in accordance with equation (28). The linear adder 26₃ adds the codesa'₁ and b₁ to output the basic code mate a according to equation (29).Similarly, the second linear adder 28₃ sums the complement of the codea'₁ with the code b₁ to output the other basic code mate b in accordancewith equation (30).

The embodiment of the invention shown in FIG. 2 has somewhat of apractical advantage over the embodiment shown in FIG. 1, notwithstandingthe requirement of a time delay in each compression stage. Thisadvantage results from the elimination of all but one code sequenceinverter which, if optimum coherent compression is to be realized,cannot be a relatively simple standard last-in/first-out non-linearshift register. The sequence inverter must be synchronously timed to theinput bit stream, must separately gate out and appropriately delay eachbit of the code sequence, and then must linearly add all of the delayedbits. Minimizing the required quantity of sequence inverters for thepulse compressor is therefore very advantageous. However, none would berequired at all, if after generating an expanded code a_(n) and b_(n)with transposed codes, one of these was then sequence inverted prior totransmission where the sequence inversion could then be achieved with arelatively simple standard LIFO shift register.

Thus what has been shown and described is an improved means forimplementing a passive matched filter arrangement which compresses to alobeless impulse multiplexed noise codes that are expanded withtransposed codes of code mate pairs.

Having thus shown and described what is at present considered to be thepreferred method and means for embodying the invention, it should beunderstood that the foregoing detailed description has been made by wayof illustration and not limitation. Accordingly, all alterations,modifications and changes coming within the spirit and scope of theinvention as set forth in the appended claims are herein meant to beincluded.

I claim:
 1. Apparatus for code comprising a mated pair of multiplexed,noise-coded, digital signals (a_(i)) and (b_(i)) where the number ofbits in each said signal equals 2i comprising:a plurality of codecompressor stages connected in tandem; each said stage having means forcompressing an input mated pair connected thereto into an output matedpair having one-half the number of bits of said input mated pair andhaving the absolute value of each bit amplitude of said output signalequal to twice the absolute value of each bit amplitude of said inputsignals; the first one of said code compressor stages having first andsecond inputs connected to said input mated pair of signals (a_(i)) and(b_(i)) respectively; and the other of said code compressor stageshaving first and second inputs connected to first and second outputsrespectively of the preceeding one of said stages for connecting saidoutput mated pair thereto.
 2. Apparatus according to claim 1 andwherein:each said stage has said first input therein connected to oneinput of a first adder and to the input of a first code sequenceinverter; said second input therein connected to one input of a secondadder and to the input of a second code sequence inverter; each saidstage having a signal inverter connected between said first codesequence inverter and a second input of said second adder; said outputof said second code sequence inverter connected to a second input ofsaid first adder: and said first and second outputs of each of saidstages connected to the outputs of said first and second adders thereinrespectively.
 3. Apparatus according to claim 1 and wherein:said firststage has said first input connected to one input of a first adder andthe input of a signal inverter; said second input of said first stageconnected to the input of a code sequence inverter; said code sequenceinverter having the output therefor connected to a second input of saidfirst adder and to one input of a second adder; said signal inverterhaving the output thereof connected to a second input of said secondadder; the remaining ones of said code compressor stages each havingsaid first input therein connected to a delay means for delaying signalsa time period equal to the code length of the signal on said secondinput therein; the output of said delay means connected to one input ofa first adder and a code inverter therein; the output of said codeinverter connected to one input of a second adder therein; said secondinput being connected to a second input of each said first and secondadders; and the outputs of all said first and second adders beingconnected to said first and second inputs respectively of the succeedingcode compressor stage.